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general description the max5888 is an advanced, 16-bit, 500msps digital- to-analog converter (dac) designed to meet the demanding performance requirements of signal synthe- sis applications found in wireless base stations and other communications applications. operating from a single 3.3v supply, this dac offers exceptional dyna- mic performance such as 76dbc spurious-free dynamic range (sfdr) at f out = 40mhz. the dac supports update rates of 500msps and a power dissipation of only 250mw. the max5888 utilizes a current-steering architecture, which supports a full-scale output current range of 2ma to 20ma, and allows a differential output voltage swing between 0.1v p-p and 1v p-p . the max5888 features an integrated 1.25v bandgap reference and control amplifier to ensure high accuracy and low noise performance. additionally, a separate reference input pin enables the user to apply an exter- nal reference source for optimum flexibility and to improve gain accuracy. the digital and clock inputs of the max5888 are designed for differential low-voltage differential signal (lvds)-compatible voltage levels. the max5888 is available in a 68-lead qfn package with an exposed paddle (ep) and is specified for the extended industrial temperature range (-40? to +85?). refer to the max5887 and max5886 data sheets for pin-compatible 14- and 12-bit versions of the max5888. applications base stations: single-/multicarrier umts, cdma, gsm communications: lmds, mmds, point-to-point microwave digital signal synthesis automated test equipment (ate) instrumentation features 500msps output update rate single 3.3v supply operation excellent sfdr and imd performance sfdr = 76dbc at f out = 40mhz (to nyquist) imd = -85dbc at f out = 10mhz aclr = 73db at f out = 61mhz 2ma to 20ma full-scale output current differential, lvds-compatible digital and clock inputs on-chip 1.25v bandgap reference low 130mw power dissipation 68-lead qfn-ep package max5888 3.3v, 16-bit, 500msps high dynamic performance dac with differential lvds inputs ________________________________________________________________ maxim integrated products 1 ordering information 19-2726; rev 1; 2/03 for pricing, delivery, and ordering information, please contact maxim/dallas direct! at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. part temp range pin- package MAX5888Aegk -40 c to +85 c 68 qfn-ep* max5888egk -40 c to +85 c 68 qfn-ep* 58 59 60 61 62 54 55 56 57 63 38 39 40 41 42 43 44 45 46 47 vclk agnd b6p qfn top view dgnd dv dd dgnd b7n b7p b8n b8p b9n b9p 52 53 b10n b10p av dd fsadj refio n.c. dacref agnd av dd ioutp ioutn av dd agnd agnd av dd av dd b13n b13p b14n b14p b15n b15p dgnd dv dd sel0 n.c. 35 36 37 n.c. n.c. n.c. dv dd dgnd b0n b0p b1n vclk clkgnd clkn clkp clkgnd b1p b2n b2p b3n 48 b12p b3p 64 b6n 65 66 67 b4p b5n b5p 68 b4n 23 22 21 20 19 27 26 25 24 18 29 28 32 31 30 agnd n.c. 34 33 49 50 b11p b12n 51 b11n 11 10 9 8 7 6 5 4 3 2 16 15 14 13 12 1 pd 17 max5888 pin configuration * ep = exposed paddle.
max5888 3.3v, 16-bit, 500msps high dynamic performance dac with differential lvds inputs 2 _______________________________________________________________________________________ absolute maximum ratings electrical characteristics (av dd = dv dd = vclk = 3.3v, agnd = dgnd = clkgnd = 0, external reference, v refio = 1.25v, r l = 50 ? , i out = 20ma, t a = t min to t max , unless otherwise noted. +25 c guaranteed by production test, <+25 c guaranteed by design and characterization. typical values are at t a = +25 c.) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. av dd , dv dd , vclk to agnd................................-0.3v to +3.9v av dd , dv dd , vclk to dgnd ...............................-0.3v to +3.9v av dd , dv dd , vclk to clkgnd ...........................-0.3v to +3.9v agnd, clkgnd to dgnd....................................-0.3v to +0.3v dacref, refio, fsadj to agnd.............-0.3v to av dd + 0.3v ioutp, ioutn to agnd................................-1v to av dd + 0.3v clkp, clkn to clkgnd...........................-0.3v to vclk + 0.3v b0p/b0n b15p/b15n, sel0, pd to dgnd ...........................................-0.3v to dv dd + 0.3v continuous power dissipation (t a = +70 c) 68-lead qfn-ep (derate 30.3mw/ c above +70 c) ...3333mw thermal resistance ( ja ) ..............................................+24 c/w operating temperature range ..........................-40 c to +85 c junction temperature .....................................................+150 c storage temperature range ............................-60 c to +150 c lead temperature (soldering, 10s) ................................+300 c parameter symbol conditions min typ max units static performance resolution 16 bits MAX5888A___, measured differentially, t a +25 c -0.008 0.004 +0.008 integral nonlinearity inl max5888___, measured differentially, t a +25 c 0.006 % fs MAX5888A___, measured differentially, t a +25 c -0.006 0.002 +0.006 differential nonlinearity dnl max5888___, measured differentially, t a +25 c 0.003 % fs offset error os -0.01 0.003 +0.01 % fs offset drift 50 ppm/ c full-scale gain error ge fs external reference, t a +25 c -3.1 +1.1 % fs internal reference 100 gain drift external reference 50 ppm/ c full-scale output current i out (note 1) 2 20 ma min output voltage single ended -0.5 v max output voltage single ended 1.1 v output resistance r out 1m ? output capacitance c out 5pf dynamic performance output update rate f clk 1 500 msps f clk = 100mhz f out = 16mhz, -12db fs -158 signal-to-noise ratio to nyquist snr f clk = 200mhz f out = 80mhz, -12db fs -156 db fs/ hz f out = 1mhz, 0db fs 88 f out = 1mhz, -6db fs 89 spurious-free dynamic range to nyquist sfdr f clk = 100mhz f out = 1mhz, -12db fs 85 dbc
max5888 3.3v, 16-bit, 500msps high dynamic performance dac with differential lvds inputs _______________________________________________________________________________________ 3 electrical characteristics (continued) (av dd = dv dd = vclk = 3.3v, agnd = dgnd = clkgnd = 0, external reference, v refio = 1.25v, r l = 50 ? , i out = 20ma, t a = t min to t max , unless otherwise noted. +25 c guaranteed by production test, <+25 c guaranteed by design and characterization. typical values are at t a = +25 c.) parameter symbol conditions min typ max units f out = 10mhz, -12db fs 82 f clk = 100mhz f out = 30mhz, -12db fs 79 f out = 10mhz, -12db fs 73 f out = 16mhz, -12db fs 69 77 f out = 50mhz, -12db fs 72 f clk = 200mhz f out = 80mhz, -12db fs 66 f out = 10mhz, -12db fs 67 f out = 30mhz, -12db fs 65 f out = 50mhz, -12db fs 65 spurious-freedynamic range to nyquist sfdr f clk = 500mhz f out = 80mhz, -12db fs 63 dbc spurious-free dynamic range, 25mhz bandwidth sfdr f clk = 100mhz f out = 20mhz, -12db fs 98 dbc f out1 = 9mhz, -6db fs f clk = 100mhz f out2 = 10mhz, -6db fs -85 f ou t 1 = 49m h z, - 12d b fs 2-tone imd ttimd f clk = 300mhz f ou t 2 = 50m h z, - 12d b fs -65 dbc 4-tone imd, 1mhz frequency spacing, gsm model ftimd f clk = 300mhz f out = 32mhz, -12db fs -78 dbc adjacent channel leakage power ratio, 4.1mhz bandwidth, wcdma model aclr f clk = 184.32mhz f out = 61.44mhz 73 db output bandwidth bw -1db (note 2) 450 mhz reference internal reference voltage range v refio 1.13 1.22 1.3 v reference voltage drift tco ref 50 ppm/ c reference input compliance range v refiocr 0.125 1.250 v reference input resistance r refio 10 k ? analog output timing output fall time t fall 90% to 10% (note 3) 375 ps output rise time t rise 10% to 90% (note 3) 375 ps output voltage settling time t settle output settles to 0.025% fs (note 3) 11 ns output propagation delay t pd (note 3) 1.8 ns glitch energy 1 pv-s i out = 2ma 30 output noise n out i out = 20ma 30 pa/ hz timing characteristics data to clock setup time t setup referenced to rising edge of clock -1 ns data to clock hold time t hold referenced to rising edge of clock 1.4 ns
max5888 3.3v, 16-bit, 500msps high dynamic performance dac with differential lvds inputs 4 _______________________________________________________________________________________ electrical characteristics (continued) (av dd = dv dd = vclk = 3.3v, agnd = dgnd = clkgnd = 0, external reference, v refio = 1.25v, r l = 50 ? , i out = 20ma, t a = t min to t max , unless otherwise noted. +25 c guaranteed by production test, <+25 c guaranteed by design and characterization. typical values are at t a = +25 c.) parameter symbol conditions min typ max units data latency 4 clock cycles minimum clock pulse width high t ch clkp, clkn 0.9 ns minimum clock pulse width low t cl clkp, clkn 0.9 ns lvds logic inputs (b0n?15n, b0p?15p) differential input logic high v ih 100 mv differential input logic low v il -100 mv common-mode voltage range v com 1.125 1.375 v differential input resistance r in 85 100 125 ? input capacitance c in 5pf cmos logic inputs (pd, sel0) input logic high v ih 0.7 ? ? clock inputs (clkp, clkn) sine wave 1.5 differential input voltage swing v clk square wave 0.8 v p-p differential input slew rate sr clk (note 4) >100 v/s common-mode voltage range v com 1.5 20% v input resistance r clk 5k ? input capacitance c clk 5pf power supplies analog supply voltage range av dd 3.135 3.3 3.465 v digital supply voltage range dv dd 3.135 3.3 3.465 v clock supply voltage range v clk 3.135 3.3 3.465 v f clk = 100msps, f out = 1mhz 27 analog supply current i avdd power-down 0.3 ma f clk = 100msps, f out = 1mhz 7 ma digital supply current i dvdd power-down 6 a f clk = 100mhz, f out = 1mhz 5.6 ma clock supply current i vclk power-down 10 a
max5888 3.3v, 16-bit, 500msps high dynamic performance dac with differential lvds inputs _______________________________________________________________________________________ 5 note 1: nominal full-scale current i out = 32 ? i ref . note 2: this parameter does not include update-rate depending effects of sin(x)/x filtering inherent in the max5888. note 3: parameter measured single ended into a 50 ? termination resistor. note 4: a differential clock input slew rate of >100v/ms is required to achieve the specified dynamic performance. note 5: parameter defined as the change in midscale output caused by a 5% variation in the nominal supply voltage. parameter symbol conditions min typ max units f clk = 100msps, f out = 1mhz 130 . power dissipation p diss power-down 1 mw power-supply rejection ratio psrr av dd = vclk = dv dd = 3.3v 5% (note 5) -1 +1 % fs/v electrical characteristics (continued) (av dd = dv dd = vclk = 3.3v, agnd = dgnd = clkgnd = 0, external reference, v refio = 1.25v, r l = 50 ? , i out = 20ma, t a = t min to t max , unless otherwise noted. +25 c guaranteed by production test, <+25 c guaranteed by design and characterization. typical values are at t a = +25 c.) typical operating characteristics (av dd = dv dd = vclk = 3.3v, external reference, v refio = 1.25v, r l = 50 ? , i out = 20ma, t a = +25 c, unless otherwise noted.) 0 30 20 10 40 50 60 70 80 90 100 020 10 30 40 50 spurious-free dynamic range vs. output frequency (f clk = 100mhz) max5888 toc01 f out (mhz) sfdr (dbc) -12db fs 0db fs -6db fs 0 30 20 10 40 50 60 70 80 90 100 060 30 90 120 150 spurious-free dynamic range vs. output frequency (f clk = 300mhz) max5888 toc02 f out (mhz) sfdr (dbc) -6db fs 0db fs -12db fs 0 30 20 10 40 50 60 70 80 90 100 0 100 50 150 200 250 spurious-free dynamic range vs. output frequency (f clk = 500mhz) max5888 toc03 f out (mhz) sfdr (dbc) -6db fs 0db fs -12db fs -100 -70 -80 -90 -60 -50 -40 -30 -20 -10 0 79 8101112 2-tone intermodulation distortion (f clk = 100mhz) max5888 toc04 f out (mhz) 2-tone imd (dbm) 2 x f t1 - f t2 2 x f t2 - f t1 f t2 f t1 a out = -6db fs bw = 5mhz f t1 = 9.0252mhz f t2 = 10.0417mhz -40 -60 -50 -80 -70 -90 -100 0 2-tone imd vs. output frequency (1mhz carrier spacing, f clk = 300mhz) max5888 toc05 f out (mhz) two-tone imd (dbc) 50 25 75 100 -6db fs -12db fs -100 -70 -80 -90 -60 -50 -40 -30 -20 -10 0 77 79 78 80 81 82 2-tone intermodulation distortion (f clk = 450mhz) max5888 toc06 f out (mhz) 2-tone imd (dbm) 2 x f t1 - f t2 2 x f t2 - f t1 f t2 f t1 a out = -6db fs bw = 5mhz f t1 = 79.2114mhz f t2 = 80.0903mhz
max5888 3.3v, 16-bit, 500msps high dynamic performance dac with differential lvds inputs 6 _______________________________________________________________________________________ typical operating characteristics (continued) (av dd = dv dd = vclk = 3.3v, external reference, v refio = 1.25v, r l = 50 ? , i out = 20ma, t a = +25 c, unless otherwise noted.) 50 58 66 74 82 90 sfdr vs. temperature (f clk = 300mhz, a out = -6db fs, i out = 20ma max5888toc08 temperature ( c) sfdr (dbc) -40 10 -15 60 35 85 f out = 80mhz f out = 120mhz f out = 10mhz f out = 40mhz 0 20 40 60 80 100 sfdr vs. output frequency (f clk = 300mhz, a out = -6db fs) max5888toc07 f out (mhz) sfdr (dbc) 060 30 120 90 150 i out = 5ma i out = 20ma i out = 10ma -3.0 -1.5 0 1.5 3.0 differential nonlineartiy vs. digital input code max5888toc10 digital input code dnl (lsb) 0 30000 20000 10000 50000 40000 70000 60000 -4.5 -3.0 -1.5 0 1.5 3.0 4.5 integral nonlinearity vs. digital input code max5888toc9 digital input code inl (lsb) 0 30000 20000 10000 50000 40000 70000 60000 -100 -70 -80 -90 -60 -50 -40 -30 -20 -10 0 26 30 28 34 32 36 38 8-tone multitone power ratio plot (f clk = 300mhz, f center = 31.9702mhz) max5888 toc11 f out (mhz) 8-tone mtpr (dbm) f t2 f t6 f t3 f t7 f t4 f t8 f t1 f t5 a out = -18db fs bw = 12mhz f t1 = 28.0151mhz f t2 = 29.0405mhz f t3 = 30.0659mhz f t4 = 31.0181mhz f t5 = 33.06881mhz f t6 = 34.0209mhz f t7 = 35.0464mhz f t8 = 36.0718mhz mtpr = 72dbc 80 120 160 200 240 280 power dissipation vs. clock frequency (f out = 10mhz, a out = 0db fs, i out = 20ma) max5888toc12 f clk (mhz) power dissipation (mw) 100 300 200 400 500 116 120 124 128 132 136 power dissipation vs. supply voltage (f clk = 100mhz, f out = 10mhz, i fs = 20ma) max5888toc13 supply voltage (v) power dissipation (mw) 3.135 3.300 3.245 3.190 3.355 3.410 3.465 external reference internal reference
max5888 3.3v, 16-bit, 500msps high dynamic performance dac with differential lvds inputs _______________________________________________________________________________________ 7 pin description pin name function 1 b3p data bit 3 2 b3n complementary data bit 3 3 b2p data bit 2 4 b2n complementary data bit 2 5 b1p data bit 1 6 b1n complementary data bit 1 7 b0p data bit 0 (lsb) 8 b0n complementary data bit 0 (lsb) 9, 41, 60, 62 dgnd digital ground 10, 40, 61 dv dd digital supply voltage. accepts a supply voltage range of 3.135v to 3.465v. bypass each pin with a 0.1f capacitor to the nearest dgnd. 11, 16 vclk clock supply voltage. accepts a supply voltage range of 3.135v to 3.465v. bypass each pin with a 0.1f capacitor to the nearest clkgnd. 12, 15 clkgnd clock ground 13 clkp converter clock input. positive input terminal for the differential converter clock. 14 clkn complementary converter clock input. negative input terminal for the differential converter clock. 17 pd power-down input. pd pulled high enables the dac s power-down mode. pd pulled low allows for normal operation of the dac. this pin features an internal pulldown resistor. 18, 24, 29, 30, 32 av dd analog supply voltage. accepts a supply voltage range of 3.135v to 3.465v. bypass each pin with a 0.1f capacitor to the nearest agnd. 19, 25, 28, 31, 33, ep agnd analog ground. exposed paddle (ep) must be connected to agnd. 20 refio reference i/o. output of the internal 1.2v precision bandgap reference. bypass with a 1f capacitor to agnd. can be driven with an external reference source. 21 fsadj full-scale adjust input. this input sets the full-scale output current of the dac. for 20ma full-scale output current, connect a 2k ? resistor between fsadj and dacref. 22 dacref return path for the current set resistor. for 20ma full-scale output current, connect a 2k ? resistor between fsadj and dacref. 23, 34 38 n.c. not connected. do not connect to these pins. do not tie these pins together. 26 ioutn complementary dac output. negative terminal for differential current output. the full-scale output current range can be set from 2ma to 20ma. 27 ioutp dac output. positive terminal for differential current output. the full-scale output current range can be set from 2ma to 20ma. 39 sel0 mode select input sel0. set high to activate the segment shuffling function. since this pin features an internal pulldown resistor, it can be left open or pulled low to disable the segment-shuffling function. see segment shuffling in the detailed description section for more information. 42 b15p data bit 15 (msb) 43 b15n complementary data bit 15 (msb) 44 b14p data bit 14
max5888 3.3v, 16-bit, 500msps high dynamic performance dac with differential lvds inputs 8 _______________________________________________________________________________________ detailed description architecture the max5888 is a high-performance, 16-bit, current- steering dac (figure 1) capable of operating with clock speeds up to 500mhz. the converter consists of sepa- rate input and dac registers, followed by a current- steering circuit. this circuit is capable of generating differential full-scale currents in the range of 2ma to 20ma. an internal current-switching network in combi- nation with external 50 ? termination resistors convert the differential output currents into a differential output voltage with a peak-to-peak output voltage range of 0.1v to 1v. an integrated 1.2v bandgap reference, con- trol amplifier, and user-selectable external resistor determine the data converter s full-scale output range. reference architecture and operation the max5888 supports operation with the on-chip 1.2v bandgap reference or an external reference voltage source. refio serves as the input for an external, low- impedance reference source, and as the output if the dac is operating with the internal reference. for stable operation with the internal reference, refio should be decoupled to agnd with a 0.1f capacitor. due to its limited output drive capability refio must be buffered with an external amplifier, if heavier loading is required. the max5888 s reference circuit (figure 2) employs a control amplifier, designed to regulate the full-scale current i out for the differential current outputs of the dac. configured as a voltage-to-current amplifier, the output current can be calculated as follows: i out = 32 ? i refio - 1lsb i out = 32 ? i refio - (i out / 2 16 ) where i refio is the reference output current (i refio = v refio /r set ) and i out is the full-scale output current of the dac. located between fsadj and dacref, r set is the reference resistor, which determines the amplifi- er s output current for the dac. see table 1 for a matrix of different i out and r set selections. pin name function 45 b14n complementary data bit 14 46 b13p data bit 13 47 b13n complementary data bit 13 48 b12p data bit 12 49 b12n complementary data bit 12 50 b11p data bit 11 51 b11n complementary data bit 11 52 b10p data bit 10 53 b10n complementary data bit 10 54 b9p data bit 9 55 b9n complementary data bit 9 56 b8p data bit 8 57 b8n complementary data bit 8 58 b7p data bit 7 59 b7n complementary data bit 7 63 b6p data bit 6 64 b6n complementary data bit 6 65 b5p data bit 5 66 b5n complementary data bit 5 67 b4p data bit 4 68 b4n complementary data bit 4 pin description (continued)
max5888 3.3v, 16-bit, 500msps high dynamic performance dac with differential lvds inputs _______________________________________________________________________________________ 9 analog outputs (ioutp, ioutn) the max5888 outputs two complementary currents (ioutp, ioutn) that can be operated in a single- ended or differential configuration. a load resistor can convert these two output currents into complementary single-ended output voltages. the differential voltage existing between ioutp and ioutn can also be con- verted to a single-ended voltage using a transformer or a differential amplifier configuration. if no transformer is used, the output should have a 50 ? termination to the analog ground and a 50 ? resistor between the outputs. although not recommended, because of additional noise pickup from the ground plane, for single-ended 1.25v reference current-steering dac function selection block agnd sel0 dgnd dv dd refio refadj clkn clkp pd av dd ioutp ioutn segment shuffling/latch decoder lvds receiver input/latch 16 differential digital input b0 through b15 max5888 figure 1. simplified max5888 block diagram r set (k ? ) full-scale current i out (ma) reference current i ref (a) calculated 1% eia std output voltage v ioutp/n * (mv p-p ) 2 62.5 19.2 19.1 100 5 156.25 7.68 7.5 250 10 312.5 3.84 3.83 500 15 468.75 2.56 2.55 750 20 625 1.92 1.91 1000 table 1. i out and r set selection matrix based on a typical 1.200v reference voltage * terminated into a 50 ? load.
max5888 3.3v, 16-bit, 500msps high dynamic performance dac with differential lvds inputs 10 ______________________________________________________________________________________ operation ioutp should be selected as the output, with ioutn connected to agnd. note that a single-ended output configuration has a higher 2nd-order harmonic distortion at high output frequencies than a differential output configuration. figure 3 displays a simplified diagram of the internal output structure of the max5888. clock inputs (clkp, clkn) the max5888 features a flexible differential clock input (clkp, clkn) operating from separate supplies (vclk, clkgnd) to achieve the lowest possible jitter performance. the two clock inputs can be driven from a single-ended or a differential clock source. for sin- gle-ended operation, clkp should be driven by a logic source, while clkn should be bypassed to agnd with a 0.1f capacitor. the clkp and clkn pins are internally biased to 1.5v. this allows the user to ac-couple clock sources directly to the device without external resistors to define the dc level. the input resistance of clkp and clkn is >5k ? . see figure 4 for a convenient and quick way to apply a differential signal created from a single-ended source (e.g., hp 8662a signal generator) and a wideband transformer. these inputs can also be driven from an lvds-compatible clock source; however, it is recom- mended to use sinewave or ac-coupled ecl drive for best performance. data timing relationship figure 5 shows the timing relationship between differ- ential, digital lvds data, clock, and output signals. the max5888 features a 1.4ns hold, a -1ns setup, and a 1.8ns propagation delay time. there is a 4-clock-cycle latency between clkp/clkn transitioning high/low and ioutp/ioutn. lvds-compatible digital inputs (b0p?15p, b0n?15n) the max5888 features lvds receivers on the bus input interface. these lvds inputs (b0p/n through b15p/n) allow for a low-differential voltage swing with low con- stant power consumption across a large range of 0.1 f 1.25v reference 10k ? i ref r set dacref fsadj refio i ref = v refio /r set current-steering dac av dd ioutp ioutn figure 2. reference architecture, internal reference configuration i out i out ioutn ioutp current sources current switches av dd figure 3. simplified analog output structure single-ended clock source (e.g., hp 8662a) 1:1 wideband rf transformer performs single-ended to differential conversion. to dac clkp 0.1 f 0.1 f clkn clkgnd 25 ? 25 ? figure 4. differential clock signal generation
max5888 3.3v, 16-bit, 500msps high dynamic performance dac with differential lvds inputs ______________________________________________________________________________________ 11 frequencies. their differential characteristic supports the transmission of high-speed data patterns without the negative effects of electromagnetic interference (emi). all max5888 lvds inputs feature on-chip termi- nation with differential 100 ? resistors. see figure 6 for a simplified block diagram of the lvds inputs. a common-mode level of 1.25v and an 800mv differen- tial input swing can be applied to these inputs. segment shuffling (sel0) segment shuffling can improve the sfdr of the max5888. the improvement is most pronounced at higher output frequencies and amplitudes. note that an improvement in sfdr can only be achieved at the cost of a slight increase in the dac s noise floor. pin sel0 controls the segment-shuffling function. if sel0 is pulled low, the segment-shuffling function of the dac is disabled. sel0 can also be left open, because an internal pulldown resistor helps to deacti- vate the segment-shuffling feature. to activate the max5888 segment-shuffling function, sel0 must be pulled high. power-down operation (pd) the max5888 also features an active-high power-down mode, which allows the user to cut the dac s digital current consumption to less than 6a and the analog current consumption to less than 0.3ma. a single pin (pd) is used to control the power-down mode (pd = 1) or reactivate the dac (pd = 0) after power-down. enabling the power-down mode of the max5888 allows the overall power consumption to be reduced to less than 1mw. the max5888 requires 10ms to wake up from power-down and enter a fully operational state. applications information differential coupling using a wideband rf transformer the differential voltage existing between ioutp and ioutn can also be converted to a single-ended volt- age using a transformer (figure 7) or a differential amplifier configuration. using a differential transformer coupled output, in which the output power is limited to 0dbm, can optimize the dynamic performance. however, make sure to pay close attention to the trans- former core saturation characteristics when selecting a transformer for the max5888. transformer core satura- tion can introduce strong 2nd-harmonic distortion, especially at low output frequencies and high signal b0 to b15 clkp iout n - 1 n n + 1 n + 2 n - 6 n - 4 n - 2 n - 3 n - 3 t setup t hold t pd t ch t cl figure 5. detailed timing relationship 100 ? b0p?15p b0n?15n dq d q clock to decode logic figure 6. simplified lvds-compatible input structure
max5888 3.3v, 16-bit, 500msps high dynamic performance dac with differential lvds inputs 12 ______________________________________________________________________________________ amplitudes. it is also recommended to center tap the transformer to ground. if no transformer is used, each dac output should be terminated to ground with a 50 ? resistor. additionally, a 100 ? resistor should be placed between the outputs (figure 8). if a single-ended unipolar output is desirable, ioutp should be selected as the output, with ioutn ground- ed. however, driving the max5888 single ended is not recommended since additional noise is added (from the ground plane) in such configurations. the distortion performance of the dac depends on the load impedance. the max5888 is optimized for a 50 ? double termination. it can be used with a transformer output as shown in figure 7 or just one 50 ? resistor from each output to ground and one 50 ? resistor between the outputs. this produces a full-scale output power of up to 0dbm depending on the output current setting. higher termination impedance can be used at the cost of degraded distortion performance and increased output noise voltage. adjacent channel leakage power ratio (aclr) testing for cdma- and wcdma-based base station transceiver systems (bts) the transmitter sections of bts applications serving cdma and wcdma architectures must generate carri- ers with minimal coupling of carrier energy into the adja- cent channels. similar to the gsm/edge model (see the multitone testing for gsm/edge applications section in the applications section), a transmit mask (tx mask) exists for this application. the spread-spectrum modula- tion function applied to the carrier frequency generates a spectral response, which is uniform over a given band- width (up to 4mhz) for a wcdma-modulated carrier. a dominant specification is aclr, a parameter which reflects the ratio of the power in the desired carrier band to the power in an adjacent carrier band. the specification covers the first two adjacent bands, and is measured on both sides of the desired carrier. according to the transmit mask for cdma and wcdma architectures, the power ratio of the integrated carrier channel energy to the integrated adjacent channel energy must be >45db for the first adjacent carrier slot (aclr 1) and >50db for the second adjacent carrier slot (aclr 2). this specification applies to the output of the entire transmitter signal chain. the requirement for only the dac block of the transmitter must be tighter, with a typical margin of >15db, requiring the dac s aclr 1 to be better than 60db. adjacent channel leak- age is caused by a single-spread spectrum carrier, which generates intermodulation (im) products between the frequency components located within the carrier band. the energy at one end of the carrier band generates im products with the energy from the oppo- site end of the carrier band. for single-carrier wcdma modulation, these imd products are spread 3.84mhz over the adjacent sideband. four contiguous wcdma max5888 t2, 1:1 t1, 1:1 v out , single ended wideband rf transformer t2 performs the differential to single-ended conversion. 50 ? 100 ? 50 ? ioutp ioutn b0 b15 16 av dd dv dd vclk agnd dgnd clkgnd figure 7. differential to single-ended conversion using a wideband rf transformer max5888 50 ? 100 ? 50 ? ioutp ioutn b0 b15 16 av dd dv dd vclk agnd dgnd clkgnd outp outn figure 8. max5888 differential output configuration
max5888 3.3v, 16-bit, 500msps high dynamic performance dac with differential lvds inputs ______________________________________________________________________________________ 13 carriers spread their im products over a bandwidth of 20mhz on either side of the 20mhz total carrier band- width. in this four-carrier scenario, only the energy in the first adjacent 3.84mhz side band is considered for aclr 1. to measure aclr, drive the converter with a wcdma pattern. make sure that the signal is backed off by the peak-to-average ratio, such that the dac is not clipping the signal. aclr can then be measured with the aclr measurement function built into your spectrum analyzer. figure 9 shows the aclr performance for a single wcdma carrier (f clk = 184mhz, f out = 61mhz) applied to the max5888 (including measurement sys- tem limitations*). in this illustration, the adjacent chan- nel spectrum clearly falls into the noise floor of the measurement system. this is identified by the flattening of the spectrum into the noise floor, instead of the slop- ing shoulders expected for an aclr plot. the mea- sured aclr 1 value of 73db is therefore understating the actual performance of the part, which is better than 74db after eliminating the noise floor limitations caused by the instrument. figure 10 illustrates the aclr test results for the max5888 with a four-carrier wcdma signal at an out- put frequency of 61mhz and sampling frequency of 184mhz. again, the noise floor of the instrument restricts the signal s real dynamic range of the signal, and the measured aclr 1 understates the actual by more than 2.5db. considerable care must be taken to ensure accurate measurement of this parameter. multitone testing for gsm/edge applications the transmitter sections of multicarrier base station transceiver systems for gsm/edge usually present communication dac manufacturers with the difficult task of providing devices with higher resolution, while simultaneously reducing noise and spurious emissions over a desired bandwidth. to specify noise and spurious emissions from base sta- tions, a gsm/edge tx mask is used to identify the dac requirements for these parameters. this mask shows that the allowable levels for noise and spurious emis- sions are dependent on the offset frequency from the transmitted carrier frequency. the gsm/edge mask and its specifications are based on a single active car- rier with any other carriers in the transmitter being dis- abled. specifications displayed in figure 11 support per-carrier output power levels of 20w or greater. lower output power levels yield less stringent emission requirements. for gsm/edge applications, the dac demands spurious emission levels of less than -80dbc for offset frequencies 6mhz. spurious products from the dac can combine with both random noise and spu- rious products from other circuit elements. the spuri- ous products from the dac should therefore be backed off by 6db more to allow for these other sources and still avoid signal clipping. * note that due to their own im effects and noise limitations, spectrum analyzers introduce aclr errors, which can falsify the me asure- ment. for a single-carrier aclr measurement greater than 70db, these measurement limitations are significant, becoming even mor e restricting for multicarrier measurement. before attempting an aclr measurement, it is recommended consulting application notes pro- vided by major spectrum analyzer manufacturers that provide useful tips on how to use their instruments for such tests. -125 -100 -110 -120 -90 -80 -70 -60 -50 -30 -40 output power (dbm) -25 3.5mhz/div f center = 61.44mhz f clk = 184.32mbps aclr = 73db figure 9. aclr for wcdma modulation, single carrier -130 -100 -110 -120 -90 -80 -70 -60 -50 -30 -40 3.5mhz/div f center = 61.44mhz f clk = 184.32mbps aclr = 65db output power (dbm) figure 10. aclr for wcdma modulation, four carriers
max5888 3.3v, 16-bit, 500msps high dynamic performance dac with differential lvds inputs 14 ______________________________________________________________________________________ the number of carriers and their signal levels with respect to the full scale of the dac are important as well. unlike a full-scale sine wave, the inherent nature of a multitone signal contains higher peak-to-rms ratios, raising the prospect for potential clipping, if the signal level is not backed off appropriately. if a transmitter operates with four/eight in-band carriers, each individ- ual carrier must be operated at less than -12db fs/-18db fs to avoid waveform clipping. the noise density requirements (table 2) for a gsm/edge-based system can again be derived from the system s tx mask. with a worst-case noise level of -80dbc at frequency offsets of 6mhz and a measure- ment bandwidth of 100khz, the minimum noise density per hertz is calculated as follows: snr min = -80dbc - 10 ? log 10 (100 ? 10 3 hz) snr min = -130dbc/hz since random dac noise adds to both the spurious tones and to random noise from other circuit elements, it is rec- ommended reducing the specification limits by about 10db to allow for these additional noise contributions while maintaining compliance with the tx mask values. other key factors in selecting the appropriate dac for the tx path of a multicarrier gsm/edge system is the converter s ability to offer superior imd and mtpr perfor- mance. multiple carriers in a designated band generate unwanted intermodulation distortion between the individ- ual carrier frequencies. a multitone test vector usually consists of several equally spaced carriers, usually four, with identical amplitudes. each of these carriers is rep- resentative of a channel within the defined bandwidth of interest. to verify mtpr, one or more tones are removed such that the intermodulation distortion perfor- mance of the dac can be evaluated. nonlinearities associated with the dac create spurious tones, some of which may fall back into the area of the removed tone, limiting a channel s carrier-to-noise ratio. other spurious components falling outside the band of inter- est can also be important, depending on the system s spectral mask and filtering requirements. going back to the gsm/edge tx mask, the imd specification for adja- cent carriers varies somewhat among the different gsm standards. for the pcs1800 and gsm850 standards, the dac must meet an average imd of -70dbc. table 3 summarizes the dynamic performance require- ments for the entire tx signal chain in a four-carrier gsm/edge-based system and compares the previous- ly established converter requirements with a new-gen- eration high dynamic performance dac. the four-tone mtpr plot in figure 12 demonstrates the max5888 s excellent dynamic performance. the center frequency (f center = 32mhz) has been removed to allow detection and analysis of intermodulation or spuri- ous components falling back into this empty spot from adjacent channels. the four carriers are observed over a 12mhz bandwidth and are equally spaced at 1mhz. each individual output amplitude is backed off to -12db fs. under these conditions, the dac yields an mtpr performance of -78dbc. number of carriers carrier power level (db fs) dac noise density requirement (db fs/hz) 2 -6 -146 4 -12 -152 8 -18 -158 table 2. gsm/edge noise requirements for multicarrier systems specification system transmitter output levels dac requirements with margins max5888 specifications sfdr 80dbc 86dbc 98dbc* snr -130dbc/hz -152db fs/hz -156db/hz imd -70dbc -75dbc -78dbc carrier amplitude n/s -12db fs -12db fs table 3. summary of important ac performance parameters for multicarrier gsm/edge systems * measured within a 25mhz window.
max5888 3.3v, 16-bit, 500msps high dynamic performance dac with differential lvds inputs ______________________________________________________________________________________ 15 grounding, bypassing, and power-supply considerations grounding and power-supply decoupling can strongly influence the performance of the max5888. unwanted digital crosstalk may couple through the input, refer- ence, power supply, and ground connections, affecting dynamic performance. proper grounding and power- supply decoupling guidelines for high-speed, high-fre- quency applications should be closely followed. this reduces emi and internal crosstalk that can significant- ly affect the dynamic performance of the max5888. use of a multilayer printed circuit (pc) board with sepa- rate ground and power-supply planes is recommend- ed. high-speed signals should run on lines directly above the ground plane. since the max5888 has sepa- rate analog and digital ground buses (agnd, clkgnd, and dgnd, respectively), the pc board should also have separate analog and digital ground sections with only one point connecting the two planes. digital signals should be run above the digital ground plane and analog/clock signals above the analog/clock ground plane. digital signals should be kept as far away from sensitive analog inputs, reference inputs sense lines, common-mode input, and clock inputs as practical. a symmetric design of clock input and ana- log output lines is recommended to minimize 2nd-order harmonic distortion components and optimize the dac s dynamic performance. digital signal paths should be kept short and run lengths matched to avoid propagation delay and data skew mismatches. the max5888 supports three separate power-supply inputs for analog (avdd), digital (dvdd), and clock (vclk) circuitry. each avdd, dvdd, and vclk input should at least be decoupled with a separate 0.1f capacitor as close to the pin as possible and their opposite ends with the shortest possible connection to the corresponding ground plane (figure 13). try to minimize the analog and digital load capacitances for optimized operation. all three power-supply voltages should also be decoupled at the point they enter the pc board with tantalum or electrolytic capacitors. ferrite beads with additional decoupling capacitors forming a pi network could also improve performance. the analog and digital power-supply inputs av dd , vclk, and dv dd of the max5888 allow a supply volt- age range of 3.3v 5%. o -30 -60 -70 -73 -75 -80 -90 0.2 0.4 0.6 1.2 1.8 6.0 imd requirement: < -70dbc 30khz 100khz measurement bandwidth transmitter edge inband outband worst-case noise level amplitude (dbc) frequency offset from carrier (mhz) figure 11. gsm/edge tx mask -100 -70 -80 -90 -60 -50 -40 -30 -20 -10 0 26 30 28 34 32 36 38 4-tone multitone power ratio plot (f clk = 300mhz, f center = 31.9702mhz) f out (mhz) 4-tone mtpr (dbm) f t2 f t3 f t4 f t1 a out = -12db fs bw = 12mhz f t1 = 30.0659mhz f t2 = 31.0181mhz f t3 = 33.0688mhz f t4 = 34.0209mhz figure 12. 4-tone mtpr test results, f center = 32mhz, f clk = 300mhz
max5888 3.3v, 16-bit, 500msps high dynamic performance dac with differential lvds inputs 16 ______________________________________________________________________________________ the max5888 is packaged in a 68-lead qfn-ep package (package code: g6800-4), providing greater design flexibility, increased thermal efficiency**, and optimized ac performance of the dac. the exposed pad (ep) enables the user to implement grounding techniques, which are necessary to ensure highest per- formance operation. the ep must be soldered down to agnd. in this package, the data converter die is attached to an ep lead frame with the back of this frame exposed at the package bottom surface, facing the pc board side of the package. this allows a solid attachment of the package to the pc board with standard infrared (ir) flow soldering techniques. a specially created land pat- tern on the pc board, matching the size of the ep (6mm ? 6mm), ensures the proper attachment and grounding of the dac. designing vias*** into the land area and implementing large ground planes in the pc board design allow for highest performance operation of the dac. an array of at least 4 ? 4 vias ( 0.3mm diameter per via hole and 1.2mm pitch between via holes) is rec- ommended for this 68-lead qfn-ep package. static performance parameter definitions integral nonlinearity (inl) integral nonlinearity is the deviation of the values on an actual transfer function from either a best straight line fit (closest approximation to the actual transfer curve) or a line drawn between the end points of the transfer func- tion, once offset and gain errors have been nullified. for a dac, the deviations are measured at every individual step. differential nonlinearity (dnl) differential nonlinearity is the difference between an actual step height and the ideal value of 1 lsb. a dnl error specification of less than 1 lsb guarantees no missing codes and a monotonic transfer function. ferrite bead av dd 1 f10 f47 f analog power- supply source ferrite bead dv dd 1 f10 f47 f digital power- supply source ferrite bead vclk 1 f10 f47 f clock power- supply source av dd agnd max5888 b0 b15 16 0.1 f dgnd 0.1 f vclk clkgnd 0.1 f outp outn dv dd bypassing?ac level bypassing?oard level figure 13. recommended power-supply decoupling and bypassing circuitry ** thermal efficiency is not the key factor, since the max5888 features low-power operation. the exposed pad is the key element to ensure a solid ground connection between the dac and the pc board s analog ground layer. *** vias connect the land pattern to internal or external copper planes. it is important to connect as many vias as possible to the analog ground plane to minimize inductance.
max5888 3.3v, 16-bit, 500msps high dynamic performance dac with differential lvds inputs ______________________________________________________________________________________ 17 offset error the offset error is the difference between the ideal and the actual offset point. for a dac, the offset point is the step value when the digital input is at midscale. this error affects all codes by the same amount. gain error a gain error is the difference between the ideal and the actual full-scale output voltage on the transfer curve, after nullifying the offset error. this error alters the slope of the transfer function and corresponds to the same percentage error in each step. settling time the settling time is the amount of time required from the start of a transition until the dac output settles its new output value to within the converter s specified accuracy. glitch energy glitch impulses are caused by asymmetrical switching times in the dac architecture, which generates unde- sired output transients. the amount of energy that appears at the dac s output is measured over time and usually specified in the pv-s range. dynamic performance parameter definitions signal-to-noise ratio (snr) for a waveform perfectly reconstructed from digital sam- ples, the theoretical maximum snr is the ratio of the full- scale analog output (rms value) to the rms quantization error (residual error). the ideal, theoretical minimum can be derived from the dac s resolution (n bits): snr db = 6.02 db ? n + 1.76 db however, noise sources such as thermal noise, refer- ence noise, clock jitter, etc., affect the ideal reading; therefore, snr is computed by taking the ratio of the rms signal to the rms noise, which includes all spec- tral components minus the fundamental, the first four harmonics, and the dc offset. spurious-free dynamic range (sfdr) sfdr is the ratio of rms amplitude of the carrier fre- quency (maximum signal components) to the rms value of their next-largest distortion component. sfdr is usually measured in dbc and with respect to the car- rier frequency amplitude or in db fs with respect to the dac s full-scale range. depending on its test condition, sfdr is observed within a predefined window or to nyquist. two-/four-tone intermodulation distortion (imd) the two-tone imd is the ratio expressed in dbc (or db fs) of either input tone to the worst 3rd-order (or high- er) imd products. note that 2nd-order imd products usually fall at frequencies that can be easily removed by digital filtering; therefore, they are not as critical as 3rd-order imds. the two-tone imd performance of the max5888 was tested with the two individual input tone levels set to at least -6db fs and the four-tone perfor- mance was tested according to the gsm model at an output frequency of 32mhz and amplitude of -12db fs. adjacent channel leakage power ratio (aclr) commonly used in combination with wcdma, aclr reflects the leakage power ratio in db between the measured power within a channel relative to its adja- cent channel. aclr provides a quantifiable method of determining out-of-band spectral energy and its influ- ence on an adjacent channel when a bandwidth-limited rf signal passes through a nonlinear device. chip information transistor count: 10,629 process: cmos
max5888 3.3v, 16-bit, 500msps high dynamic performance dac with differential lvds inputs maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circuit patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 18 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ? 2003 maxim integrated products printed usa is a registered trademark of maxim integrated products. package information (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline information, go to www.maxim-ic.com/packages .) maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circuit patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 18 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ? 2003 maxim integrated products printed usa is a registered trademark of maxim integrated products. package information (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline information, go to www.maxim-ic.com/packages .) 68l qfn, 10x10x09,eps *max5888 package code *

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